A systematic approach to circuit design and analysis: classification of Two-VCCS Circuits

This paper discusses a systematic approach to the design and analysis of circuits, using a transconductor or voltage controlled current source (VCCS) as a building block. It is shown that two independent Kirchhoff relations among the VCCS voltages and currents play a crucial role in establishing a unique transfer function in two-port circuits with two VCCSs. A class of two VCCS circuits is defined, which can be subdivided into three main classes and 14 subclasses, based on different imposable sets of two Kirchhoff relations. The classification is useful for circuit synthesis and analysis, as it reveals all the basically different ways to exploit two VCCS's, and allows for a unified analysis of classes of circuits. To exemplify this, all complementary metal-oxide-semiconductor (CMOS) V-I converter kernels, based on two matched MOS transistor (MOST)-VCCSs, are generated and analyzed with respect to distortion. It is shown that dozens of published transconductor circuits can be classified in only four classes, with essentially different distortion behavio

Systematic Comparison of HF CMOS Transconductors

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments

Systematic Generation of Transconductance based Variable Gain Amplifier Topologies

A systematic method for the generation of variable gain amplifier topologies is proposed. The generation is based on voltage controlled current sources (VCCSs) modelling saturated MOS transistors, resistors or combinations of these elements. It is shown that many alternative circuit topologies can be generated, that would not easily have been found in an intuitive way. Simulation results shown that significant differences in performance occur, with various mixes of specific strong and weak points. The set of alternative topologies can be used as a circuit topology database for analogue CAD system

Thermal Noise Canceling in LNAs: A Review

Most wide-band amplifiers suffer from a fundamental trade-off between noise figure NF and source impedance matching, which limits NF to values typically above 3dB. Recently, a feed-forward noise canceling technique has been proposed to break this trade-off. This paper reviews the principle of the technique and its key properties. Although the technique has been applied to wideband CMOS LNAs, it can just as well be implemented exploiting transconductance elements realized with other types of transistors

Distortion Cancellation via Polyphase Multipath Circuits

The central question of this paper is: can we enhance the spectral purity of nonlinear circuits with the help of polyphase multipath circuits. Polyphase multipath circuits are circuits with two or more paths that exploit phase differences between the paths to cancel unwanted signals. It turns out that it is very well possible to cancel distortion products produced by a nonlinear circuit. Unfortunately, there are also some spectral components that cannot be cancelled with the polyphase multipath circuits. In this paper tables are presented that can easily be used to predict which spectral components are cancelled and which are not cancelled for a certain polyphase multipath circuit

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation

A Differential 4-Path Highly Linear Widely Tunable On-Chip Band-Pass Filter

A passive switched capacitor RF band-pass filter with clock controlled center frequency is realized in 65nm CMOS. An off-chip transformer which acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3dB bandwidth of 35MHz and can be tuned from 100MHz up to 1GHz. IIP3 is better than 19dBm, P1dB=2dBm and NF<;5.5dB at Pdiss=2mW to 16mW.\u

A Discrete-Time Mixing Receiver Architecture with Wideband Image and Harmonic Rejection for Software-Defined Radio

A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock\ud generation

A wideband high-linearity RF receiver front-end in CMOS

This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 /spl mu/m CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise figure of 6.5 dB, +1 dBm IIP/sub 3/, +34.5 dBm IIP/sub 2/ and <50 kHz 1/f-noise corner frequency